Session: 06-05 Thermal Management Applications 2

Paper Number: 97204

97204 - Power Envelope Analysis for the Thermal Optimization of a Chiplet Module 

As Moore’s law approaches the physical limit of the critical size on the chip, designers are looking to build devices in the vertical direction, namely out of the plane where the chip sits, using 2.5D and 3D IC packaging solutions. Thermal management becomes critical and presents a design challenge when the power dissipation level and the level of complexity in package architecture increases. Under this circumstance, exploring the integrated thermal management from the package level to the board level is needed to ensure the performance and reliability of high power components.

In this paper, the thermal performances of a Chiplet module designed with various configurations, such as monolithic die, 2.5D and 3D stacked die, are studied and compared.  The pros and cons of each configuration are studied with a finite difference simulation scheme.  The operations of the Chiplet module using different configurations inside a server system with different thermal interface materials were simulated.  In order to enhance the thermal performance, a vapor chamber and lidless packages are also considered and discussed. 

A novel power management method is developed to help circuit engineers to predict the reliability of silicon in the early stage of the design.  The method considers the resistor networks of the components to calculate the temperature distribution of the dies to form a 2D or 3D power envelop plots.  As circuit engineers select the power magnitudes of dies, the distances to threshold surface on the power envelop plots are calculated to predict or determine the thermal reliability. The developed power management method is applicable to a chiplet module with many dies, and we have expanded the methodology to a system having more than 3 dies. An advanced histogram study is also used to compare the differences in thermal reliability among many configurations or different power magnitudes of chiplet modules.

With the work described in this paper, we will provide a unique numerical scheme and power management tool to better understand the thermal behaviors of the Chiplet module.  The work provides crucial insights for the development of better and more reliable next generation Chiplet modules.   

Presenting Author: Eric Ouyang JCET Group